1. Field of the Invention
The present invention relates to a network device in a packet switched network and more particularly to a pipeline architecture implemented in the network device.
2. Description of the Related Art
A packet switched network may include one or more network devices, such as a Ethernet switching chip, each of which includes several modules that are used to process information that is transmitted through the device. Specifically, the device includes an ingress module, a Memory Management Unit (MMU) and an egress module. The ingress module includes switching functionality for determining to which destination port a packet should be directed. The MMU is used for storing packet information and performing resource checks. The egress module is used for performing packet modification and for transmitting the packet to at least one appropriate destination port. One of the ports on the device may be a CPU port that enables the device to send and receive information to and from external switching/routing control entities or CPUs.
As packets enter the device from multiple ports, they are forwarded to the ingress module where switching and other processing are performed on the packets. Thereafter, the packets are transmitted to one or more destination ports through the MMU and the egress module. According to a current switching system architecture, when the packet enters one of the modules in the device, the module generates operation instructions and processes a single operation in more than one processing cycle. In this switching system architecture, processing functions in each module of the device is de-centralized. As such, the same processing functions may be implemented in more than one location in each module. This slows down the performance of the device and makes processing by the device more costly.